Programmable at the core
A GPU-class architecture designed to support evolving workloads—not a fixed-function endpoint.
PROGRAMMABLE ACCELERATED COMPUTING
One architecture.
FPGA to chip.
DIRAC is our foundation for a new class of GPU and accelerator infrastructure—programmable, memory-led, and engineered as one system from software to silicon.
NowFPGA-based compute products.
NextScaling through systems and later purpose-built silicon
01 / THE IDEA
The GPU became the engine of modern computing. We are rethinking that engine.
Every engineering step—from deterministic execution and HBM locality to live Voice and Chat—is part of a larger platform. DIRAC is implemented today in FPGA-based compute products, with a path through servers and racks to later purpose-built silicon.
02 / TECHNOLOGY
Built as a complete
compute system.
WORKLOADS
AIGraphicsScienceData
SOFTWARE
Models + ApplicationsTools, compilers, runtime and orchestration
DIRAC
Programmable Compute IPDeterministic execution, data movement and memory locality
SYSTEM
Card → Server → Rack → ChipOne architecture expressed at every scale
Memory-led by design
Compute, HBM and data movement are designed together so the whole system can do useful work.
Exact before expansive
We qualify deterministic dense execution first, creating a trustworthy base for broader capabilities.
03 / DIFFERENCE
Architecture is not a component.
It is the whole path.
Hardware and software, together
The runtime, workload mapping, compute engines, memory paths and physical implementation evolve as one design.
Proof over promises
Exact outputs, deterministic semantics and physical qualification come before performance claims.
A platform, not a point product
The same architectural foundation connects today's FPGA-based compute products to larger systems and later purpose-built silicon.
04 / WHAT DIRAC ENABLES
Wherever accelerated computing matters, DIRAC can fit.
Voice and Chat are our first live applications. The platform ambition spans the same broad workload universe served by modern GPUs—expanded deliberately as the architecture and software stack mature.
Training + inference
Foundation models, fine-tuning, recommendation, search, vision and generative AI.
Initial focusGraphics + gaming
Rendering, real-time graphics, virtual production, visualization and digital twins.
RoadmapScientific computing
Simulation, numerical methods, engineering analysis, research and discovery.
RoadmapMedia + interaction
Voice, conversational systems, video, imaging and content processing.
Voice live firstRobotics + autonomy
Perception, planning and responsive compute from the edge to the data centre.
Future platformAnalytics + infrastructure
Parallel analytics, databases, security, cloud services and high-throughput computing.
Future platform05 / HARDWARE FAMILY
From personal compute
to infrastructure.
Nine expressions of the Mastiṣka hardware vision. A shared design language connects desktop systems, accelerator modules and large-scale infrastructure to robotics and automotive compute.
A signature in titanium.
Bright brushed titanium finishes, polished edges and diagonal ventilation give the family a common identity. Graphite structures add depth; restrained teal accents mark the details.
Desktop
A compact desktop concept for local AI experimentation and development.
Workstation
An expandable tower concept for demanding development, research and creative workloads.
Server
A modular rackmount concept for integrating accelerators into shared compute systems.
Rack
A cabinet-scale concept bringing compute, service access and cooling together.
Cluster
A multi-rack vision for coordinating compute, networking and shared cooling infrastructure.
PCIe Card
An add-in accelerator concept for integration into compatible host systems.
OAM Module
An OAM-style module concept with a tall heatsink assembly, retention frame and service handle.
Robotics
A mountable edge-compute concept with accessible camera, sensor and control connections.
Automotive
A rugged enclosure concept exploring onboard compute packaging and sealed connections.
THE FOUNDATION / DIRAC
FPGA-based compute products are the current implementation of DIRAC and are undergoing exact physical qualification. Purpose-built silicon is a later implementation path for the same architecture. These form studies explore how the platform could take shape across systems and applications.
06 / THE GREATER PUZZLE
Build the product.
Build the system.
Build the future.
Today's engineering is the first layer of a much larger strategy: a sovereign, programmable accelerated-computing platform created in the UAE and built for global scale.
- NOWDeterministic dense executionExact single-token qualification on U50
- NEXTApplications and systemsVoice, Chat, resident decoding and server integration
- SCALEMemory and rack architectureEfficient traffic, deployment and scale-out
- FUTUREPurpose-built siliconThe DIRAC architecture in chip form
07 / EXPERIENCE + BUILD